18.6.10

Keil RealView Microcontroller Development Kit & RealView Real-Time Library v.4.1




Keil RealView  Microcontroller Development Kit & RealView Real-Time Library v.4.10

The software development RealView Microcontroller Development Kit (MDK ARM) combines the company Keil compiler C / C + + ARM RealView IDE and Keil uVision.

Year: 2010
Version: 4.10
Developer: Keil ?, an ARM ® Company
Platform: Windows
Compatibility with Vista: Yes (set to Win7 x64 Ultimate build 7600 - no problems)
Medician: Yes

This product gives developers a multifunctional development environment optimized to work with a broad line of microcontrollers based on the core ARM. MDK ARM provides device support, based on the ARM7, ARM9 and Cortex M3 manufacturers such as Analog Devices, Atmel, Freescale, Luminary, OKI, NXP, Samsung, Sharp, STMicroelectronics and TI. Using the MDK ARM reduces the design cycle and significantly reduce time-to-market. MDK ARM - the ideal tool for standardized industrial projects with a developed system debugging and support for real-time.

Library RL ARM - RealView ® RealTime Library
? RTX Real Time Kernel - a full-featured operating system real-time RTX Keil, which manages the CPU time semaphores (resource allocation), events (for task synchronization), and mailboxes (for communication between tasks). RTX is easily configured using the configuration file.
? TCP / IP Networking Suite - a communication module based on the stack TCP / IP, specially adapted for embedded applications. It includes TCP and UDP-sockets, PPP and SLIP interfaces, DNS, Telnet, TFTP, SMTP, built-in Web server and CGI with password protection. The stack works with Ethernet, and serial (modem). Configured examples are intended to work on a few standard demonstration boards.
? Flash File System - a system that allows you to save files in Flash, ROM or RAM. This is useful in decisions that require a large amount of memory for data storage or systems with internet interfaces, HTTP or FTP.
? USB Device Interface - drivers for USB, which allows you to connect standard devices such as HID or Mass Storage.
? CAN Interface - in RTX Keil library includes CAN, which provide a powerful and simple interface for different controllers CAN.

Library RL-ARM is designed for typical problems that confront the developer, and allows you to:
? manage multiple tasks on one CPU;
? control the timing of the task;
? communicate and configure the interaction between different programs in the system;
? Provide access to the Internet via Ethernet or serial connection (modem);
? Implement a built-in web server which includes CGI-scripts;
? Implement a E-mail via Simple Mail Transfer Protocol (SMTP).

Changes in RV MDK ARM 4.10 compared with 4.03a

[ARM Processor Support]
MDK now includes the RealView Compilation Tools version 4.0.0.728 with Cortex-M4 and Cortex-R4 support.
[ARM Processor Support]
Added: simulation for Cortex-M4 Processor core including DSP and FPU extensions.
[New Device Support]
NXP LPC1759, and LPC1769 devices.
[Device Simulation]
Simulation support added for NXP LPC11xx, LPC13xx, and LPC17xx series.
[Checksum Utility]
Added: ELFDWT utility creates boot checksum for NXP LPC11xx, LPC13xx, and LPC17xx device series. Usage is:
C: \ Keil \ ARM \ BIN \ ELFDWT elf_file.AXF
The checksum creation can be automated in µVision by entering in the dialog Project - Options for Target - User, Run User Programs After Build / Rebuild, Run # 1:
$ K \ ARM \ BIN \ ELFDWT.EXE # L
When this command is enabled µVision calls the ELFDWT utility and the required checksum gets inserted into the AXF linker output file. Note that this process is not needed when programs are downloaded using ULINK. ULINK automatically adds the checksum during Flash programming.
[Target Debugging]
Updated: support for ST-Link USB-JTAG debugger. The STLinkIIIUSBDriver.dll debug driver has been replaced by STLinkUSBDriver.dll in folder .. \ ARM \ STLink \. The flash file loader stm32f10xLoader.bin for STM32F10x devices has been added in folder .. \ ARM \ STLink \
[Target Debugging]
Updated: Luminary lmidk-agdi.dll to version 37.0.0.0.
[Target Debugging]
Updated: Segger's J-Link driver for ARM devices to version 4.11.9.0 that solves problems with Micrium µC / evaluation STM32FF-107 board.
[Target Debugging]
Added: support for Cortex-M0 devices when Segger's J-Link and J-Trace debugger is used.
[Board Support]
Added: USBHID and USBMem examples for Atmel's ATSAM3S device in folder .. \ ARM \ Boards \ Atmel \ ATSAM3S-EK \.
[Board Support]
Added: Blinky, BlinkyCAN, LCD_BLinky, RTX_Blinky, USBHID, and USBMem examples for NXP's LPC2929 device in folder .. \ ARM \ Boards \ Keil \ MCB2929 \.

The changes in the RL-ARM 4.10 compared with 4.05

[RTX - Problems Solved]
Corrected: potential wrong return value of os_mbx_send () function in Cortex-M library.
[TCPnet - Enhancements]
Added: support for Cortex-M1 devices. Free TCP_CM1.lib and debug TCPD_CM1.lib library have been added.
Added: a SNMP Agent implementation and SNMP_demo example for various evaluation boards. SNMP version 1 with trap messages is supported.
Added: a Gratuitous ARP implementation. If this feature is enabled, the embedded host broadcasts an ARP notification at startup or if local IP address changed.
Added: a new file type php-script, file extension php [text / html] to the Web server.
[TCPnet - Problems Solved]
Added: MSS option (maximum segment size) to SYN packet for outgoing TCP connections. Because this option was missing, PC used reduced segment size of 536 bytes in communication.
Corrected: auto disconnect problem in FTP Server during large file transfer.
Corrected: a problem in WEB Server. It failed to load pages from SPI or parallel flash.
Corrected: a Null Modem driver problem. It failed to connect in client mode, if connect request was issued delayed from application reset.
Corrected: a problem in PPP module which sometimes fails to connect.
[FlashFS - Enhancements]
Added: Support for SDHC Cards.
[CAN - Problems Solved]
Corrected: function CAN_set now returns error code.
[FCARM - Enhancements]
Added: a simple compression for Cascading Style Sheet files.
Improved: compression ratio for Java Script files.
[FCARM - Problems Solved]
Corrected: a problem in Java and CGI script compression.

Install crack:
In Keil:
1. File-> License Management, copy the contents of the CID
2. Run the crack, choose what generic license Target-> ARM, Prof.Devkit / RealView MDK
In the CID insert that copied in Keil
Click Generate
3. Copy the licensed paste in Keil in the field of New License ID Code (LIC), click Add LIC
4. Repeat pp.2-3 for all the required products
5. Glad result

Download:




Keil RealView Microcontroller Development Kit & RealView Real-Time Library v.4.10

Keil RealView Microcontroller Development Kit & RealView  Real-Time Library v.4.10

The software development RealView Microcontroller Development Kit (MDK ARM) combines the company Keil compiler C / C + + ARM RealView IDE and Keil uVision.

Year: 2010
Version: 4.10
Developer: Keil ™, an ARM ® Company
Platform: Windows
Compatibility with Vista: Yes (set to Win7 x64 Ultimate build 7600 - no problems)
Medician: Yes

This product gives developers a multifunctional development environment optimized to work with a broad line of microcontrollers based on the core ARM. MDK ARM provides device support, based on the ARM7, ARM9 and Cortex M3 manufacturers such as Analog Devices, Atmel, Freescale, Luminary, OKI, NXP, Samsung, Sharp, STMicroelectronics and TI. Using the MDK ARM reduces the design cycle and significantly reduce time-to-market. MDK ARM - the ideal tool for standardized industrial projects with a developed system debugging and support for real-time.

Library RL ARM - RealView ® RealTime Library
• RTX Real Time Kernel - a full-featured operating system real-time RTX Keil, which manages the CPU time semaphores (resource allocation), events (for task synchronization), and mailboxes (for communication between tasks). RTX is easily configured using the configuration file.
• TCP / IP Networking Suite - a communication module based on the stack TCP / IP, specially adapted for embedded applications. It includes TCP and UDP-sockets, PPP and SLIP interfaces, DNS, Telnet, TFTP, SMTP, built-in Web server and CGI with password protection. The stack works with Ethernet, and serial (modem). Configured examples are intended to work on a few standard demonstration boards.
• Flash File System - a system that allows you to save files in Flash, ROM or RAM. This is useful in decisions that require a large amount of memory for data storage or systems with internet interfaces, HTTP or FTP.
• USB Device Interface - drivers for USB, which allows you to connect standard devices such as HID or Mass Storage.
• CAN Interface - in RTX Keil library includes CAN, which provide a powerful and simple interface for different controllers CAN.

Library RL-ARM is designed for typical problems that confront the developer, and allows you to:
• manage multiple tasks on one CPU;
• control the timing of the task;
• communicate and configure the interaction between different programs in the system;
• Provide access to the Internet via Ethernet or serial connection (modem);
• Implement a built-in web server which includes CGI-scripts;
• Implement a E-mail via Simple Mail Transfer Protocol (SMTP).

Changes in RV MDK ARM 4.10 compared with 4.03a

[ARM Processor Support]
MDK now includes the RealView Compilation Tools version 4.0.0.728 with Cortex-M4 and Cortex-R4 support.
[ARM Processor Support]
Added: simulation for Cortex-M4 Processor core including DSP and FPU extensions.
[New Device Support]
NXP LPC1759, and LPC1769 devices.
[Device Simulation]
Simulation support added for NXP LPC11xx, LPC13xx, and LPC17xx series.
[Checksum Utility]
Added: ELFDWT utility creates boot checksum for NXP LPC11xx, LPC13xx, and LPC17xx device series. Usage is:
C: \ Keil \ ARM \ BIN \ ELFDWT elf_file.AXF
The checksum creation can be automated in µVision by entering in the dialog Project - Options for Target - User, Run User Programs After Build / Rebuild, Run # 1:
$ K \ ARM \ BIN \ ELFDWT.EXE # L
When this command is enabled µVision calls the ELFDWT utility and the required checksum gets inserted into the AXF linker output file. Note that this process is not needed when programs are downloaded using ULINK. ULINK automatically adds the checksum during Flash programming.
[Target Debugging]
Updated: support for ST-Link USB-JTAG debugger. The STLinkIIIUSBDriver.dll debug driver has been replaced by STLinkUSBDriver.dll in folder .. \ ARM \ STLink \. The flash file loader stm32f10xLoader.bin for STM32F10x devices has been added in folder .. \ ARM \ STLink \
[Target Debugging]
Updated: Luminary lmidk-agdi.dll to version 37.0.0.0.
[Target Debugging]
Updated: Segger's J-Link driver for ARM devices to version 4.11.9.0 that solves problems with Micrium µC / evaluation STM32FF-107 board.
[Target Debugging]
Added: support for Cortex-M0 devices when Segger's J-Link and J-Trace debugger is used.
[Board Support]
Added: USBHID and USBMem examples for Atmel's ATSAM3S device in folder .. \ ARM \ Boards \ Atmel \ ATSAM3S-EK \.
[Board Support]
Added: Blinky, BlinkyCAN, LCD_BLinky, RTX_Blinky, USBHID, and USBMem examples for NXP's LPC2929 device in folder .. \ ARM \ Boards \ Keil \ MCB2929 \.

The changes in the RL-ARM 4.10 compared with 4.05

[RTX - Problems Solved]
Corrected: potential wrong return value of os_mbx_send () function in Cortex-M library.
[TCPnet - Enhancements]
Added: support for Cortex-M1 devices. Free TCP_CM1.lib and debug TCPD_CM1.lib library have been added.
Added: a SNMP Agent implementation and SNMP_demo example for various evaluation boards. SNMP version 1 with trap messages is supported.
Added: a Gratuitous ARP implementation. If this feature is enabled, the embedded host broadcasts an ARP notification at startup or if local IP address changed.
Added: a new file type php-script, file extension php [text / html] to the Web server.
[TCPnet - Problems Solved]
Added: MSS option (maximum segment size) to SYN packet for outgoing TCP connections. Because this option was missing, PC used reduced segment size of 536 bytes in communication.
Corrected: auto disconnect problem in FTP Server during large file transfer.
Corrected: a problem in WEB Server. It failed to load pages from SPI or parallel flash.
Corrected: a Null Modem driver problem. It failed to connect in client mode, if connect request was issued delayed from application reset.
Corrected: a problem in PPP module which sometimes fails to connect.
[FlashFS - Enhancements]
Added: Support for SDHC Cards.
[CAN - Problems Solved]
Corrected: function CAN_set now returns error code.
[FCARM - Enhancements]
Added: a simple compression for Cascading Style Sheet files.
Improved: compression ratio for Java Script files.
[FCARM - Problems Solved]
Corrected: a problem in Java and CGI script compression.

Install crack:
In Keil:
1. File-> License Management, copy the contents of the CID
2. Run the crack, choose what generic license Target-> ARM, Prof.Devkit / RealView MDK
In the CID insert that copied in Keil
Click Generate
3. Copy the licensed paste in Keil in the field of New License ID Code (LIC), click Add LIC
4. Repeat pp.2-3 for all the required products
5. Glad result



Download:



OR



http://hotfile.com/dl/38763603/91cf6c4/MDK.RL.ARM.HLP.html

http://hotfile.com/dl/38763639/6d36569/MDK.RL.ARM.HLP.html

http://hotfile.com/dl/38763641/fd66eaa/MDK.RL.ARM.HLP.html




OR



http://hotfile.com/dl/38681023/33ab39a/MDK.RL.ARM.HLP.html

http://hotfile.com/dl/38681054/284b4fd/MDK.RL.ARM.HLP.html

http://hotfile.com/dl/38681055/063ffd1/MDK.RL.ARM.HLP.html

Keil C51 v.9.01 Compiler + uVision 4 IDE

Keil C51 v.9.01 Compiler + uVision 4 IDE

Complete Keil IDE for development of embedded apps with 8051 (and derivates) microcontroller in C and/or assembly.

Pic says more than 1000 words:

Keil C51 v.9.01 Compiler + uVision 4 IDE




9.6.10

MICROWIND + DSCH COMPLETE WITH EXAMPLES ( Full Version with 6 metal layers)

microwind
Design FlowMICROWIND supports entire front-end to back-end design flow.
For front-end designing, we have DSCH (digital schematic editor) which posses in-built pattern based simulator for digital circuits. User can also build analog circuits and convert them into SPICE files and use 3rd party simulators like WinSpice or pSPICE.
DSCH can convert the digital circuits into Verilog file which can be further synthesized for FPGA/CPLD devices of any vendor. The same Verilog file can be compiled for layout conversion in MICROWIND.
The back-end design of circuits is supported by MICROWIND. User can design digital circuits and compile here using Verilog file. MICROWIND automatically generates a error free CMOS layout. Although this place-route is not optimized enough as we do not indulge in complex place & route algorithms.
User can also create CMOS layout of their own using compile one line Verilog syntax or custom build the layouts by manual drawing.
The CMOS layouts can be verified using inbuilt mix-signal simulator and analyzed further for DRC, crosstalks, delays, 2D cross section, 3D veiw, etc.
MICROWIND is truly integrated EDA software encompassing IC designs from concept to completion, enabling chip designers to design beyond their imagination. MICROWIND integrates traditionally separated front-end and back-end chip design into an integrated flow, accelerating the design cycle and reduced design complexities.
It tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction and verification – providing an innovative education initiative to help individuals to develop the skills needed for design positions in virtually every domain of IC industry.

MICROWIND  +  DSCH  COMPLETE  WITH

EXAMPLES   ( CLICK  TO  DOWNLOAD)

 or

CLICK HERE TO DOWNLOAD – MICROWIND V3.1 only

 

 

MICROWIND LAYOUT TIPS

Tips on the finger Tips:
In this post we will be looking at various design optimization tips.
The courtesy to most of these tips are SSN sir. Thank you sir.

1.  While drawing the layouts, its best practice to have a single Vdd/Vss rail running.
How do we do this?
Draw a simple metal rail. Give Vdd/Vss to it and tap it wherever you need.
So far we haven't come across this. But in the future layouts, we will be making use of this.

2.  Avoid digging unnecessary wells.
Yeah its pretty simple for us to draw as many n well as possible. But implementing this at industry level is not possible. In industry they go for laying all p devices in a single n well. You may notice that we have used the same practice in design of Transmission Gate.

3.  Avoid using poly for routing.
Though we have made use of poly for routing in design of TG, its not a good practice. Its better to use metal for this purpose. Use of metal will reduce resistance.

4.  More tips will follow based upon inputs from experts.

MICROWIND Tutorial Part 7 : Design and Layout of D Flip Flop




The D flip flop shown above is very much different from what we have learnt so far. We have designed it using Nand nor or some other basic gates. But this is completely different.

You can also see that the circuit is like cascading of two similar blocks. Block one includes M1, M2 and the first 2 inverters. The rest of the circuit is the repetition of the first part.
 
Now, why all this unnecessary fuss? Just to make our life simple. If we draw the first part, then we just need to do our Ctrl+C and Ctrl+V to get the second part. As simple as that.

Back to business: As you can see in the schematic, the circuit involves only two basic elements. An nMOS and an inverter. Basically you need to draw only these two and half of your headache is over. (No kidding, I swear J )

step 1:
The first step is of course opening the Microwind.


Step 2:
From the palette click on the Moss generator and click Generate device. Check the lambda box (bottom right). Make the Width MOS equal to 4. Now click on Generate device. Click bindass at any place on the screen. We get an nMOS.


Step 3:
You can see that the clock which we are using is of two types. One is clk and the next is its complement. That is clk_bar. For that we need an extra inverter. (Other than the four visible). I won’t be showing you how to draw and inverter. You can refer to the previous tutorial to get the idea regarding that. We will be directly inserting it. (Cool eh?).

Go to file>Insert Layout. Browse to the previously drawn inverter and here you are.

You should be able to see the screen somewhat like this:



Insert another inverter. This is Inv 1. You can refer the schematic. This inverter is connected to the output of the nMOS M1.
We need to name them as we draw. This will make lesser confusions.


Step 4:
Half the work is over. The only thing that we need to do is placing them properly. Copying and pasting them on the right area in the right manner. You owe me a treat for this simplicity.
We will be drawing everything in a single well. This will reduce the delay and make it a best choice for the counters and register designs.
We need to take a little care now. Remember that we need to maintain a minimum of 4 lambda distance between adjacent metal rails.
So, be little careful while placing. Keep doing DRC at each step to make sure that you haven’t ended up doing it wrong.

The layouts placing:
  1. Place the Inverter for inverting the clock at extreme left. (It’s not visible in the schematic, but we need to draw it for inverting the clock and getting clk_bar.
  2. Now, everything else will be according to the schematic. Place a pass transistor, i.e. an nMOS (M1) at a distance of 4λ from the inverter.
  3. To the right of this MOS, we have another inverter named Inv 1. Place it at a distance of 4λ from it. Please make sure that all nMOS and pMOS are at the same level.
  4. The output of this Inv 1 inverter is connected to the input of Inv 2 inverter. So we need to place Inv 2 to the right of Inv 1 at a distance of 4λ. (If you are getting confused scroll up and see the schematic)
  5. The output of Inv2 is connected as input to pass transistor M2. So, place a pass transistor nMOS M2 to the right of Inv 2.
 
At this point the layout should look somewhat like this.



The intermediate file can be found here:


Step 5:

As you can make out, we have just done with placing. We need to connect the devices now. Also note that, we have not drawn the second half. Once we are done with the connection, we will duplicate first half. (Both first and the second stages are identical).

Follow this convention:

The vertical routing should be done with metal 2.
The horizontal routing to be done with metal 1.
Note that you should use Metal 1 to Metal 2 contact to connect to metal 1 and metal 2. (It can be found in the palette)
Care should be taken while connecting a polysilicon layer to metal 2 layers. A polysilicon layer cannot be connected to metal 2 layers directly. First, it has to be connected to metal 1. And then it has to be connected to metal 2.
With the above things in our mind, we will proceed with the connections.
 
After the connections, the layout will look somewhat like this.



You can even download this intermediate file and analyze it.


Step 6:
It’s time to go for stage 2. Copy the layout, just before first inverter and place it to the right of the existing layout.
This creates the second stage.
Again do the necessary connections and your layout is ready.


The final layout will look similar to this.



You can find the same over here:
The output waveforms looks like this:


You can cascade this layout in the manner you want and create various registers and counters.

Have  a  great   time

MICROWIND Tutorial Part 6 : Design and VLSI layout of Schmitt Trigger circuit.

Schmitt Trigger. (Never omit the "c" and "t" from the name of this circuit).
Yes, very soon we are back with a hot tutorial on Schmitt trigger. As usual, we will be providing the layout and simulation waveforms. Some of them are really sleeping off by the time we are done with the explanation, so we are cutting short the explanation and just giving pictorial hints so that you can draw on your own. Reffer back to the previous tutorial incase you need some basic guidance.

In electronics, a Schmitt trigger is a comparator circuit that incorporates positive feedback.
When the input is higher than a certain chosen threshold, the output is high; when the input is below another (lower) chosen threshold, the output is low; when the input is between the two, the output retains its value. The trigger is so named because the output retains its value until the input changes sufficiently to trigger a change. This dual threshold action is called hysteresis, and implies that the Schmitt trigger has some memory. In fact, the Schmitt trigger is a bistable multivibrator.

Schmitt trigger devices are typically used in open loop configurations for noise immunity and closed loop positive feedback configurations to implement multivibrators.(Courtesy: Wikipedia)
You can read the entire article over here.

Here is the schematic. Please go through the schematic properly. The naming conventions used in the schematic(for naming the MOS devices) are retained in the layout for readability.



The desing is very simple. Using the MOS generator place few n and p device and provide proper routing.
Here is the explainatory layout of Schmitt Trigger Circuit:



The output waveforms (voltage vs time) can be observed as follows:



But we are less interested in this. We want to see the hysteresis curve. To viewe the hysteresis curve follow the instructions:
1. Click on Voltage vs Voltage at the bottom of the simulation screen. (Marked with red circle in the next figure)
2. Tick the Hysteresis right at the right corner of the screen. (Again it is highlighted in the next figure)
3. Click on Reset followed by More.
You are done with Schmitt Trigger and you should be able to see the hysteresis curve as follows.



Final Schmitt Trigger Layout:



Have a great time

MICROWIND Tutorial Part 5 : Three (3) Input NAND gate

The schematic and stick diagram of 3 input nand gate looks something like this:



Please post a comment if you want to know the working of the three input nand gate. I will be more than happy to explain.

Step by step layout for 3 input nand gate.

1.     1.   Draw a single pMOS from MOS generator (available in palette)



2.     2.  Select on units in lambda (underlined in the following figure) Keep the    length as 2λ and width as 4λ.
3.    
3.  3.  Copy and place them side by side or just create two more pMOS

4.   4.  Place them beside each other at a distance of 4λ.(refer figure). Note that we need to draw them in parallel, as shown in the schematic.




5.       Now we need nMOS in series. You can of course use MOS generator and extend and draw the polysilicon sticks as shown below



6.     5. By this time we have 3 pmos and 3 nmos generated. Join the corresponding gates. Give Vcc and Vdd and the input signals.

7.       The final diagram should look like one below.



8.       
WWe are done again.


9.   The waveforms observed are:




    Have a great time.

MICROWIND Tutorial Part 4: Design, Layout and Application of CMOS Buffer

You can get a detailed idea of buffer here




 
 
Here is a logic diagram of buffer. As you can see, it is basically two inverters connected in series. This but obiviously results in no change in the output. (Complement of Complemented signal is the original signal). Then why use it?
 
Not all the time in a circuit we connect Vdd(Poser supply) to each and every node. This is because they dont need it. (because of the design). So, after a certain length of devices, the logic levels starts degrading. The high level starts reducing from that of Vdd value. Such a degradation causes noisy output and many error. Therefore the signal needs boosting. This boosting is provided by the buffer. 
In few circuits, it can be used to hold the value of a signal for certain duration.
It is used and a separation element between two different circuitry to eliminate cross talk or unwanted noise.
Enough of applications? If you need more, comment to this article. I will be glad to post few more.
I will not be going in much detail regarding the layout of the buffer. You can reffer to part 2 (design of the inverter) to get a detailed design viewe of the inverter.
 
I will be just posting the steps and the final layout.
 
Step1: (Not open the favourite Microwind window..blah blah blah)
Make a copy of the inverter circuit which you have drawn. Open the copy Microwind>File>Open. Browse to the layout and open it.
You have got one inverter. We need the next one.
 
 
Step 2:
Shortcut 1: Import an inverter. Go to File>Insert Layout browse to the inverter and import it.
Shortcut 2: In the top menu, click on Copy element. Drag the mouse holding the left button over the layout till its completely selected. Release left mouse button. You should be able to see a dotted layout exactly same as the one you have just copied. Place it away. If you happen to commit a mistake, Ctrl+U will undo it. :). The recommended spacing between them is 7lambda. You may do DRC once to find the exact spacing.
 
 
Step3:
Routing:
Ahem. Forgot to write almost final step :). Yes, we are almost done (again).
Here we will be using Vdd and Vss for both the inverters. This is as good as supplying 2 power supplies. For example, we have a single UPS for the whole computer. This is like supplying separate UPS for monitor and CPU.
We are not that rich, or are we?:).
So, what we do is draw single rail at the top of the layout, and give a single Vdd to it. Later, we can tap Vdd from it. We do the same for Vss.
Now, we need to connect the output of the first inverter to the input of the second. This can be done in two ways. Using polysilicon (because the distance is less, if the distance is more, it introduces unnecessary patasitics) or using metal.
 
I have used metal. Connect the layers. Do the dew( I mean DRC). Thats it. The layout should look something like this:
 



Press the simulation button. You should get the waveforms as shown in the fugure. If you dont, check the contacts and debug it. All the best.
 





Have a cup of coffe and be ready for the next session.
See you soon.
Keep watching this space for more.
Have a nice day.

Microwind Tutorial Part3: Design of Transmission Gate (Import layout, save time)

We are back this time with a tutorial on layout of transmission gate (TG).
 

(Should you have any basic doubts, refer back to the previous posts.)


Transmission gate is basically used to avoid logic degradation. The nMOS passes logic low very efficiently but degrades high logic, where as pMOS passes logic high satisfactorily but degrades logic low.

To overcome the above problems we go for transmission gates. Here the nMOS and pMOS both are connected together with their source and drain terminals. A control signal switches on either of the devices (means either nMOS or pMOS depending on weather the logic is high or low).
Here is the schematic:



You can see that it requires an inverter to complement the control signal A.
Now we shall frame a vague problem definition at our hand. We need to design a TG and supply inverted signal to the nMOS and pMOS using an inverter.


Step 1:
Open our favorite window of Microwind.;)


 
Step 2:
So far we have drawn the nMOS on pMOS devices manually. Let us see how we can utilize the inbuilt function.

From the palette click on MOS generator. (looks like an nMOS symbol). A window will pop up. Here you can specify various parameters. For the present design, we will consider the default values. Note that nMOS is automatically selected in this dialogue box.  Click on Generate device and place it by clicking on the substrate (black background). The red highlighted circles depict it.




In a similar manner we need to place a pMOS device. To do that, click on MOS generator, select pMOS, click on generate device and click somewhere above nMOS.




Step 3:
Aligning the devices.
In the part 1 of the tutorial I have shown how to move the devices or layouts from one position to another. That was a crude method. It does not have any control and things are done based upon the movement of mouse. Let us do it a systematic way.

From the top menu click on Edit>Move step by step. Now highlight the device which you need to move (hold the left mouse button and drag the mouse till the layout is completely selected). You should be able to see the following window:




Move left or right or up or down till they are properly aligned. Maintain a certain distance between the devices to obey the DRC. Make sure that you do DRC once after placing them.
Tip: You can directly pres Ctrl+M to move in this manner.


Step4:
Half the design is done now. (Yes, so soon).
We need an inverter to give the direct and complemented signals to the TG. We have already drawn an inverter in Part 2 of the tutorial. We can import it over here and use it directly.

This step is very important. You will be using it more frequently as you will be drawing more complex layouts.

In the top menu got to File> Import Layout. A window will pop up. Browse to the destination where you have stored the file. Select and click open. Viola! Its very much there.




We can use this inverter for our design but I prefer taking width of pMOS twice that of nMOS (why?).

I included this step to make you familiar with the import command.
Let us build an inverter the same way we built the TG. That is using MOS generator. I won’t be going in detail of that.
Place the inverter to the left of TG. Make sure that the distance between the metals is at least 8λ.
Your design should look something like this:



Step 5:
Now we need to supply the direct and inverted signals. I have done it using poly. You can even do it using metal. But if metal is used more area will be consumed, you need to place the devices further apart and you need to use minimum of 3λ width metal.
After the connections (routing) the layout is:



Step 6:
You are almost done now. We just need to give a finishing touch to layout. Connect Vdd and Vss to the inverter. (Not to TG).

In Step 4, we have generated inverter. But again the p device and n device have same width; we need to make the n device with half of p device. Do it using the gun or shoot tool. (Delete some layout.).


Complete the missing metal and poly contacts. Do the DRC once more. Satisfy the design details.
Check if all the contacts are proper. (Explained in detail in Part 2).


Step 7: (Final Step).
Apply the clock signal to the input of inverter and next clock to the input of TG.
Apply an eye (Visible node) to the output of the TG. The complete TG is at your service!



We are finally ready to click the simulation button. Click on it bindaas and you are done with it.
I have shown the outputs. In the next simulation I have interchanged the clocks of TG and inverter to understand the working.
 







Have a nice day.

MICROWIND Tutorial Part 2: Design of an Inverter

Welcome to the Part 2 of the basic layout tutorial. In the following section, I will be giving various shortcut methods, tips and tricks. We shall design an inverter. Our aim will is to adhere to the design rules using minimum possible area.

I strongly recommend reading Part 1 thoroughly before trying this. It will make you familiar with the terms.


Step 1: 
Open the Microwind. (Refer Part 1 for details).Before we get started, let’s brush up the basics of Lambda based design rules. I don’t suggest memorizing them, because we have them at hand. But you need to be familiar with the frequent rules (such as width of layers, spacing etc). However you can find the completed design rules built in the program.On the main tab, Click File>Property. A window will popup. Click on Detail of design rule button. Viola! You have them all in detail!
(You should be able to see the following window). Scroll down. At the bottom you should be able to see the frequently used rules. (This is for 6 metal processes. You may see a smaller list if you have selected a different foundry. No need to worry. The basic layers remain the same.)

(Click on the image to enlarge)
I will note down few of them which we will be using for this design. (Highlighted red). I suggest you to note down the same. The spacing shown is between the similar layers. The spacing between different layers may vary. But we always have DRC (Design Rule Check) to see if we are right.
Step 2:
We shall first draw p+ diffusion. We already know from the rules that it should be minimum of 4λ X 4λ. (Try drawing smaller than this and run DRC. You will become familiar with this.)
But wait, if we draw a diffusion of 4 λ by 4 λ, we won’t be able to make a proper transistor by laying polysilicon. (Minimum width of the polysilicon is 2 λ). So, we need to resize it. Click on the resize tool. (Marked with red circle). Stretch the mouse with left button clicked on the horizontal edge. (Refer to Part 1, resizing the image). Stretch it for around say 8λ and release the button. The actual minimum width required will be 12 λ (4 λ each for two contacts+ 4 λ spacing between each contacts= 8+4 = 12 λ. Note that the poly will be laid between the contact. The minimum width of poly should be 2 λ. It comfortably lies between the contacts. Illustration follows.)

(Click on the image to enlarge)

(Diffusion after stretching. Only partial diagram is shown)
Step 3:
Selecting polysilicon from the palette, draw the polysilicon layer exactly at the center of the diffusion. (Horizontal center. Poly should be vertical). Note that I have extended poly 3λ. This is to comply with the design rule. (The extra poly surrounding the diffusion should be more than 3λ).

Step 4:
Select the n-well from the palette and draw the N-well. (I love the color and pattern.) I have drawn it arbitrarily.

To make sure that we are following the design rules, click on DRC.
As you can see, the design rule says that “The extra nwell surrounding the diffp is less than 6λ.” You can directly click on the nwell and stretch it to a next level. Perform the DRC again to see if everything is fine before proceeding to the next step. One strange behavior of DRC is that, at the first click it points to the error, but even if the error is not corrected, the error message goes off. To recheck, you need to click again. One good thing about it is that, it also shows the scale. So that you can stretch or resize accordingly.
Step 5:
We are ready to draw the n diffusion now. Click on n+diffusion from the palette and draw it below p+. Keep the size same. (You can even keep it half of p+ diffusion, but since we have drawn the p+ diffusion of 4λ, we can not draw this diffusion less than that). Also maintain the distance between nwell and diffusion 6λ. Perform the DRC again. Your screen should look something similar to this:

Since in an inverter both the device gates are connected to each other, we need to extend the poly of the upper device to cover the lower device. We can also lay the poly from the palette. After this step the layout should be like:

Step 6:
Select metal layer from the palette. Join the devices (Source and Drain). Select appropriate contact from palette and click on metal-diffusion interface. Note the minimum width of the metal is maintained to 3λ. While placing the contacts, the dotted rectangle’s left edge should coincide with the left edge of the metal. Illustration:

We need to verify the contacts. Sometimes, we see the contacts, but they are not really bound. To verify, click on 2-D View. (Circled Red). Hold the left mouse button and strike diagonally over the contact. (See the dotted line on nmos). 
 

If everything goes fine, you will see the following window:

At present we are not bothered about other parameters, let us just see if there is a purple line, highlighted red. If you can see this, it means you have connected the layers successfully. If you are not able to see, then there is no need to worry. It’s not due to color blindness J close this window. Click on the connect layers button (top menu, underline yellow in last but one figure) and click on the layer you need to connect. Repeat the same for the other contact.
Step 7:
You have crossed the most rigorous part of the tutorial. If you wish to quit it now, I won’t stop. You have done 99% of it. Pat your back and let’s move ahead.
From the palette, select Vdd. Click on nwell. Again from click on vdd and then on the source of pmos. Add a contact where you have added vdd. Apply Vss to the source of the nmos in the same way. We need to apply the input to the inverter now. Select the clock from the palette and click on the poly connecting both pmos and nmos.
We should be able to see the output. For the present layout, the output will be available at the metal (joining drain and source of the devices). Click on the Visible Node (looks like an eye in the palette) and then click on the metal.
You are done now!

Step 8 (Final Step):
Click on Run Simulation button. If you have followed the tutorial properly, you will be able to see this:

You can view various simulation parameters. See the voltage vs. voltage to view the transfer characteristics.
I have uploaded the .MSK file over the following link. You can verify your design with mine and try it out.
In the next part of the tutorial, we will be learning:
  1. How to save time by using existing layout.
  2. How to Copy, paste and invert
Basically the next tutorial will be focused on design of transmission gate.