HINDAWI - International Journal of Reconfigurable Computing

Table of Contents [1–10 of 55 articles]

  1. Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures, Ludovic Devaux, Sana Ben Sassi, Sebastien Pillement, Daniel Chillet, and Didier Demigny
    Volume 2010 (2010), Article ID 390545, 15 pages
  2. Concurrent Calculations on Reconfigurable Logic Devices Applied to the Analysis of Video Images, Sergio R. Geninatti, José Ignacio Benavides Benítez, Manuel Hernández Calviño, and Nicolás Guil Mata
    Volume 2010 (2010), Article ID 962057, 8 pages
  3. Timing-Driven Nonuniform Depopulation-Based Clustering, Hanyu Liu and Ali Akoglu
    Volume 2010 (2010), Article ID 158602, 11 pages
  4. High-Speed FPGA 10's Complement Adders-Subtractors, G. Bioul, M. Vazquez, J. P. Deschamps, and G. Sutter
    Volume 2010 (2010), Article ID 219764, 14 pages
  5. Power Characterisation for Fine-Grain Reconfigurable Fabrics, Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, and Tero Rissa
    Volume 2010 (2010), Article ID 787405, 9 pages
  6. Multiloop Parallelisation Using Unrolling and Fission, Yuet Ming Lam, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, and Wayne Luk
    Volume 2010 (2010), Article ID 475620, 10 pages
  7. Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs, Bernard Girau, César Torres-Huitzil, Nikolaos Vlassopoulos, and José Hugo Barrón-Zambrano
    Volume 2009 (2009), Article ID 639249, 15 pages
  8. Speeding Up FPGA Placement via Partitioning and Multithreading, Cristinel Ababei
    Volume 2009 (2009), Article ID 514754, 9 pages
  9. Hardware Accelerated Sequence Alignment with Traceback, Scott Lloyd and Quinn O. Snell
    Volume 2009 (2009), Article ID 762362, 10 pages
  10. Selected Papers from ReCoSoC 2008, Michael Hübner, J. Manuel Moreno, Gilles Sassatelli, and Peter Zipf           Volume 2009 (2009), Article ID 894059, 2 pages
  11. Parallel Processor for 3D Recovery from Optical Flow, Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, and Miguel Arias-Estrada
    Volume 2009 (2009), Article ID 973475, 11 pages
  12. Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design, Erwan Fabiani
    Volume 2009 (2009), Article ID 923415, 11 pages
  13. An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures, F. Redaelli, M. D. Santambrogio, and S. Ogrenci Memik
    Volume 2009 (2009), Article ID 541067, 12 pages
  14. Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs, Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, and Octavio Nieto-Taladriz
    Volume 2009 (2009), Article ID 703267, 14 pages
  15. An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography, Xinyu Li and Omar Hammami
    Volume 2009 (2009), Article ID 631490, 14 pages
  16. Reducing Reconfiguration Overheads in Heterogeneous Multicore RSoCs with Predictive Configuration Management, Stéphane Chevobbe and Stéphane Guyetant
    Volume 2009 (2009), Article ID 390167, 7 pages
  17. Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs, Harold Ishebabi, Philipp Mahr, Christophe Bobda, Martin Gebser, and Torsten Schaub
    Volume 2009 (2009), Article ID 863630, 11 pages
  18. An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing, Christian Schuck, Bastian Haetzer, and Jürgen Becker
    Volume 2009 (2009), Article ID 273791, 11 pages
  19. A Hardware Filesystem Implementation with Multidisk Support, Ashwin A. Mendon, Andrew G. Schmidt, and Ron Sass
    Volume 2009 (2009), Article ID 572860, 13 pages
  20. Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware, Christophe Bobda, Kevin Cheng, Felix Mühlbauer, Klaus Drechsler, Jan Schulte, Dominik Murr, and Camel Tanougast
    Volume 2009 (2009), Article ID 161458, 9 pages

  21. FPGA Interconnect Topologies Exploration, Zied Marrakchi, Hayder Mrabet, Umer Farooq, and Habib Mehrez
    Volume 2009 (2009), Article ID 259837, 13 pages
  22. Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP, Marcel D. van de Burgwal, Pascal T. Wolkotte, and Gerard J. M. Smit
    Volume 2009 (2009), Article ID 678045, 12 pages
  23. Pipeline FFT Architectures Optimized for FPGAs, Bin Zhou, Yingning Peng, and David Hwang
    Volume 2009 (2009), Article ID 219140, 9 pages
  24. A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications, H. Ho, V. Szwarc, and T. Kwasniewski
    Volume 2009 (2009), Article ID 529512, 14 pages
  25. Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings, Knut Wold and Chik How Tan
    Volume 2009 (2009), Article ID 501672, 8 pages
  26. Software Toolchain for Large-Scale RE-NFA Construction on FPGA, Yi-Hua E. Yang and Viktor K. Prasanna
    Volume 2009 (2009), Article ID 301512, 10 pages
  27. A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems, Manuel Saldaña, Emanuel Ramalho, and Paul Chow
    Volume 2009 (2009), Article ID 376232, 9 pages
  28. Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms, Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, and Manfred Glesner
    Volume 2009 (2009), Article ID 851613, 15 pages
  29. Analysis and Design of a Context Adaptable SAD/MSE Architecture, Arvind Sudarsanam, Aravind Dasu, and Karthik Vaithianathan
    Volume 2009 (2009), Article ID 789592, 21 pages
  30. A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips, Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, and Manfred Glesner
    Volume 2009 (2009), Article ID 453970, 14 pages

  31. A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation, Fernando Martín del Campo, René Cumplido, Roberto Perez-Andrade, and A. G. Orozco-Lugo
    Volume 2009 (2009), Article ID 912301, 10 pages
  32. A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip, Diana Göhringer, Thomas Perschke, Michael Hübner, and Jürgen Becker
    Volume 2009 (2009), Article ID 395018, 11 pages
  33. An Adaptive Message Passing MPSoC Framework, Gabriel Marchesan Almeida, Gilles Sassatelli, Pascal Benoit, Nicolas Saint-Jean, Sameer Varyani, Lionel Torres, and Michel Robert
    Volume 2009 (2009), Article ID 242981, 20 pages
  34. A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime, Thilo Pionteck, Roman Koch, Carsten Albrecht, and Erik Maehle
    Volume 2009 (2009), Article ID 942930, 10 pages
  35. Multilevel Simulation of Heterogeneous Reconfigurable Platforms, Damien Picard and Loic Lagadec
    Volume 2009 (2009), Article ID 162416, 12 pages
  36. vMAGIC—Automatic Code Generation for VHDL, Christopher Pohl, Carlos Paiz, and Mario Porrmann
    Volume 2009 (2009), Article ID 205149, 9 pages
  37. A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks, Jim Harkin, Fearghal Morgan, Liam McDaid, Steve Hall, Brian McGinley, and Seamus Cawley
    Volume 2009 (2009), Article ID 908740, 13 pages
  38. High level modeling of Dynamic Reconfigurable FPGAs, Imran Rafiq Quadri, Samy Meftali, and Jean-Luc Dekeyser
    Volume 2009 (2009), Article ID 408605, 15 pages
  39. Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs, Shuli Gao, Dhamin Al-Khalili, and Noureddine Chabini
    Volume 2009 (2009), Article ID 145130, 11 pages
  40. Current Trends on Reconfigurable Computing, Jürgen Becker, Michael Hübner, Roger Woods, Philip Leong, Robert Esser, and Lionel Torres
    Volume 2008 (2008), Article ID 918525, 1 page

  41. Selected Papers from SPL 2008: Programmable Logic and Applications, Gustavo Sutter and Richard Katz
    Volume 2008 (2008), Article ID 921921, 2 pages
  42. Neuromorphic Configurable Architecture for Robust Motion Estimation, Guillermo Botella, Manuel Rodríguez, Antonio García, and Eduardo Ros
    Volume 2008 (2008), Article ID 428265, 9 pages
  43. The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units, Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip H. W. Leong, and Wayne Luk
    Volume 2008 (2008), Article ID 736203, 10 pages
  44. Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration, Omkar Dandekar, William Plishker, Shuvra S. Bhattacharyya, and Raj Shekhar
    Volume 2008 (2008), Article ID 738174, 17 pages
  45. Burst-Mode Asynchronous Controllers on FPGA, Duarte L. Oliveira, Marius Strum, and Sandro S. Sato
    Volume 2008 (2008), Article ID 926851, 10 pages
  46. Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology, Kostas Siozios, Alexandros Bartzas, and Dimitrios Soudris
    Volume 2008 (2008), Article ID 764942, 18 pages
  47. Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System, Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Jorge Rivera, and Alberto de la Mora
    Volume 2008 (2008), Article ID 634306, 9 pages
  48. On the Use of Magnetic RAMs in Field-Programmable Gate Arrays, Y. Guillemenet, L. Torres, G. Sassatelli, and N. Bruchon
    Volume 2008 (2008), Article ID 723950, 9 pages
  49. Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation, Johan Ditmar, Steve McKeever, and Alex Wilson
    Volume 2008 (2008), Article ID 674340, 14 pages
  50. An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, and Toshinori Sueyoshi
    Volume 2008 (2008), Article ID 180216, 14 pages

  51. Dynamic Hardware Development, Stephen Craven and Peter Athanas
    Volume 2008 (2008), Article ID 901328, 10 pages
  52. SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication, Sami Boukhechem and El-Bay Bourennane
    Volume 2008 (2008), Article ID 902653, 10 pages
  53. A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC, Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, and Lionel Torres
    Volume 2008 (2008), Article ID 403086, 11 pages
  54. FPGA-Based Embedded Motion Estimation Sensor, Zhaoyi Wei, Dah-Jye Lee, Brent E. Nelson, James K. Archibald, and Barrett B. Edwards
    Volume 2008 (2008), Article ID 636145, 8 pages
  55. On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays, Scott Y. L. Chin, Clarence S. P. Lee, and Steven J. E. Wilton
    Volume 2008 (2008), Article ID 751863, 13 pages

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