I strongly recommend reading Part 1 thoroughly before trying this. It will make you familiar with the terms.
Open the Microwind. (Refer Part 1 for details).Before we get started, let’s brush up the basics of Lambda based design rules. I don’t suggest memorizing them, because we have them at hand. But you need to be familiar with the frequent rules (such as width of layers, spacing etc). However you can find the completed design rules built in the program.On the main tab, Click File>Property. A window will popup. Click on Detail of design rule button. Viola! You have them all in detail!
(You should be able to see the following window). Scroll down. At the bottom you should be able to see the frequently used rules. (This is for 6 metal processes. You may see a smaller list if you have selected a different foundry. No need to worry. The basic layers remain the same.)
(Click on the image to enlarge)
I will note down few of them which we will be using for this design. (Highlighted red). I suggest you to note down the same. The spacing shown is between the similar layers. The spacing between different layers may vary. But we always have DRC (Design Rule Check) to see if we are right.
We shall first draw p+ diffusion. We already know from the rules that it should be minimum of 4λ X 4λ. (Try drawing smaller than this and run DRC. You will become familiar with this.)
But wait, if we draw a diffusion of 4 λ by 4 λ, we won’t be able to make a proper transistor by laying polysilicon. (Minimum width of the polysilicon is 2 λ). So, we need to resize it. Click on the resize tool. (Marked with red circle). Stretch the mouse with left button clicked on the horizontal edge. (Refer to Part 1, resizing the image). Stretch it for around say 8λ and release the button. The actual minimum width required will be 12 λ (4 λ each for two contacts+ 4 λ spacing between each contacts= 8+4 = 12 λ. Note that the poly will be laid between the contact. The minimum width of poly should be 2 λ. It comfortably lies between the contacts. Illustration follows.)
(Click on the image to enlarge)
(Diffusion after stretching. Only partial diagram is shown)
Selecting polysilicon from the palette, draw the polysilicon layer exactly at the center of the diffusion. (Horizontal center. Poly should be vertical). Note that I have extended poly 3λ. This is to comply with the design rule. (The extra poly surrounding the diffusion should be more than 3λ).
Select the n-well from the palette and draw the N-well. (I love the color and pattern.) I have drawn it arbitrarily.
To make sure that we are following the design rules, click on DRC.
As you can see, the design rule says that “The extra nwell surrounding the diffp is less than 6λ.” You can directly click on the nwell and stretch it to a next level. Perform the DRC again to see if everything is fine before proceeding to the next step. One strange behavior of DRC is that, at the first click it points to the error, but even if the error is not corrected, the error message goes off. To recheck, you need to click again. One good thing about it is that, it also shows the scale. So that you can stretch or resize accordingly.
We are ready to draw the n diffusion now. Click on n+diffusion from the palette and draw it below p+. Keep the size same. (You can even keep it half of p+ diffusion, but since we have drawn the p+ diffusion of 4λ, we can not draw this diffusion less than that). Also maintain the distance between nwell and diffusion 6λ. Perform the DRC again. Your screen should look something similar to this:
Since in an inverter both the device gates are connected to each other, we need to extend the poly of the upper device to cover the lower device. We can also lay the poly from the palette. After this step the layout should be like:
Select metal layer from the palette. Join the devices (Source and Drain). Select appropriate contact from palette and click on metal-diffusion interface. Note the minimum width of the metal is maintained to 3λ. While placing the contacts, the dotted rectangle’s left edge should coincide with the left edge of the metal. Illustration:
We need to verify the contacts. Sometimes, we see the contacts, but they are not really bound. To verify, click on 2-D View. (Circled Red). Hold the left mouse button and strike diagonally over the contact. (See the dotted line on nmos).
If everything goes fine, you will see the following window:
At present we are not bothered about other parameters, let us just see if there is a purple line, highlighted red. If you can see this, it means you have connected the layers successfully. If you are not able to see, then there is no need to worry. It’s not due to color blindness J close this window. Click on the connect layers button (top menu, underline yellow in last but one figure) and click on the layer you need to connect. Repeat the same for the other contact.
You have crossed the most rigorous part of the tutorial. If you wish to quit it now, I won’t stop. You have done 99% of it. Pat your back and let’s move ahead.
From the palette, select Vdd. Click on nwell. Again from click on vdd and then on the source of pmos. Add a contact where you have added vdd. Apply Vss to the source of the nmos in the same way. We need to apply the input to the inverter now. Select the clock from the palette and click on the poly connecting both pmos and nmos.
We should be able to see the output. For the present layout, the output will be available at the metal (joining drain and source of the devices). Click on the Visible Node (looks like an eye in the palette) and then click on the metal.
You are done now!
Step 8 (Final Step):
Click on Run Simulation button. If you have followed the tutorial properly, you will be able to see this:
You can view various simulation parameters. See the voltage vs. voltage to view the transfer characteristics.
I have uploaded the .MSK file over the following link. You can verify your design with mine and try it out.
In the next part of the tutorial, we will be learning:
- How to save time by using existing layout.
- How to Copy, paste and invert
Basically the next tutorial will be focused on design of transmission gate.